Semiconductor storage device

ABSTRACT

A semiconductor memory device is provided for preventing a late-write from disturbing a refresh operation and also for reducing a current consumption in a write cycle with execution of the late-write. Upon a transition of an address ADD, an address transition detector circuit  101  detects this address transition. Upon receipt of a result of detection by the address transition detector circuit  101 , a state control circuit  102  judges an operation to be executed, from an output enable signal /OE and a write enable signal /WE, and then outputs any of a read statement RS, a write statement WS, and a refresh statement FS. According to a clock signal ACLK, input signals such as addresses are taken for executions of operations based on the statements.

TECHNICAL FIELD

[0001] The present invention relates to a semiconductor memory deviceconfigured to have a memory cell array including the same memory cellsas of a DRAM (Dynamic Random Access Memory) and to be operable in thesame specification as a general-purpose SRAM (static RAM).

BACKGROUND OF THE ART

[0002] A pseudo-SRAM has been known, which has a basic element of DRAMand is configured to be so operated as SRAM. The pseudo-SRAM isnon-synchronous in view of the specification, which is similar to theconventional SRAM. The pseudo-SRAM is configured to have a basic elementof DRAM. The pseudo-SRAM is so configured that operations such asrefresh being unique to DRAM are automatically performed by the insidethereof.

[0003] An example of the conventional non-synchronous semiconductormemory device configured to have a basic element of DRAM willhereinafter be described.

[0004]FIG. 1 shows an example of a configuration of the semiconductormemory device of this type. In this drawing, an address ADD is a signalgiven from the outside, and includes a row address designating a row ofa memory cell array to be described below and a column addressdesignating a column thereof.

[0005] An address input system 1 latches the address ADD and outputs aninternal address LADD. An address transition detector circuit (ATD) 2detects a transition of the internal address LADD and outputs a one-shotpulse signal OSP. An address multiplexer (MUX) 3 outputs, as an addressMADD, any one of the internal address LADD and a refresh address RADD tobe described below.

[0006] A row decoder 6 decodes the address MADD for selecting a row of amemory cell array 7. The memory cell array 70 comprises a matrix arrayof memory cells similarly to the general-purpose DRAM. A sense amplifier71 amplifies a data signal on a bit line for a read operation. A columndecoder 72 selects a column of the memory cell array 7. Evenillustration is not made, a precharge circuit for bit lines is providedaccompanying to the sense amplifier 71.

[0007] A refresh timer circuit 8G times a refresh time interval. Arefresh control circuit 8H controls a series of refresh operations andgenerates a refresh control signal REFA for controlling a refresh timingaccompanying to an external access and a refresh control signal REFB forcontrolling a self-refresh timing.

[0008] A refresh address generator circuit 8J generates an address RADD(hereinafter referred to as “refresh address”) to be used for a refreshoperation. An internal pulse generator circuit 10 generates a row enablesignal RE, a sense amplifier enable signal SE, a pre-charge enablesignal PE and a column enable signal CE.

[0009] Other than the above-described circuits, there are furtherprovided a system of circuits for controlling read and write operations,another system of circuits for generating a substrate potential of thememory cell array and still another system of circuits for read andwrite operations of data to the memory cell array.

[0010] The read and write operations and the refresh operation of thesemiconductor memory device of the prior art shown in FIG. 1 will, insequence, be described with reference to a timing chart of FIG. 2.

[0011] A. Read and Write Operations

[0012] A read operation according to an address access will be describedas one example. In this case, a chip select signal ICS and an outputenable signal /OE are set at a low level, while a write enable signal/WE is set at a high level, wherein the address ADD is applied from theoutside.

[0013] The address ADD is taken through the address input system 1 asthe internal address LADD. Except for the refresh, this internal addressLADD is supplied as the address MADD through the multiplexer 3 to therow decoder 60. At a timing defined by the row enable signal RE, the rowdecoder 60 selects one word line in the memory cell array 7, so thatdata of memory cells connected to this single row of this word line areread out onto respective bit lines. These data are amplified by thesense amplifier 71 at a timing defined by the sense amplifier enablesignal SE.

[0014] On the other hand, based on a column address (not illustrated)included in the address ADD, and at a timing defined by the columnenable signal CE, the column decoder 72 selects a bit line of the memorycell array 7, so that data on this bit line are supplied through thedata output circuit system not illustrated to the outside. Prior to theoperation of reading data from the memory cells, bit lines arepre-charged based on the pre-charge enable signal PE.

[0015] In the above-described series of read operations, upon atransition of the internal address LADD, the address transition detectorcircuit 2 detects this transition of the internal address LADD andoutputs a one-shot pulse signal OSP. By triggering this one-shot pulsesignal OSP, the internal pulse generator circuit 10 outputs, atappropriate timings, the above-described row enable signal RE, the senseamplifier enable signal SE, the pre-charge enable signal PE and thecolumn enable signal CE.

[0016] Consequently, the data are read out of the memory cell designatedby the address ADD and supplied to the outside.

[0017] B. Refresh Operation (in Read Mode)

[0018] A refresh operation in a read mode as one of the active modeswill subsequently be described with reference to a timing chart shownin. FIG. 2(a).

[0019] In the read mode, the semiconductor memory device according tothis conventional technique shows a sequential performance of both therefresh operation and the read operation in the same cycle in accordancewith the specification.

[0020] The address input system 1 latches an address A0 given from theoutside as the address ADD and then outputs the internal address LADD.The address transition detector circuit 2 detects a transition of theinternal address LADD and outputs the one-shot pulse signal OSP.

[0021] Upon receipt of the one-shot pulse signal OSP, the refreshcontrol circuit 8H starts the refresh operation. Upon the start of therefresh operation, the refresh address generator circuit 8J generatesand outputs a refresh row address R0 as the refresh address RADD. Underthe control of the refresh control circuit 8H, the address multiplexer 3supplies the refresh address RADD (the refresh row address R0) as theaddress MADD to the row decoder 60.

[0022] On the other hand, the internal pulse generator circuit 9receives an input of the refresh control signal REFB from the refreshcontrol circuit 8H, and outputs the row enable signal RE and the senseamplifier enable signal SE. The row decoder 6 receives inputs of theaddress MADD and the row enable signal RE and selects a word linedesignated by the refresh address R0 for a predetermined time perioddefined by the row enable signal RE. Data signals of the memory cellsconnected to the selected word line are amplified by the senseamplifiers and then re-stored therein, whereby the data of the memorycells for the single row designated by the refresh address R0 have beenrefreshed.

[0023] After the refresh operation has been finished for the rowdesignated by the refresh row address R0, then the read operation ismade in the same cycle. For example, the address multiplexer 3 receivesthe internal address LADD from the address input system 1 and suppliesthe internal address LADD as the address MADD to the row decoder 6. Therow decoder 6 selects the word line designated by the row address X0entered as the input address MADD. The sense amplifier 71 amplifies thedata signal appearing on the bit line in the memory cell array 7. Theamplified data are read out through a data output circuit notillustrated to the outside.

[0024] C. Refresh Operation (in Stand-by Mode)

[0025] A refresh operation in a stand-by mode will be described withreference to a timing chart shown in FIG. 2(b). In the stand-by mode,the refresh control circuit 8H times a past time from a time of the lastexternal request for access, so that if the past time becomes beyond apredetermined refresh time, then the refresh control circuit 8H outputsthe refresh control signal REFB to start the self-refresh operation.

[0026] In the above-described active mode, after the refresh operationaccompanying to the read and write operation, then the refresh controlcircuit 8H starts the timer. After the predetermined time bas past, therefresh is automatically started by triggering the timer. In either thestand-by mode and the active mode, the retention of the data is ensuredwithout starting the refresh from the outside, similarly to thegeneral-purpose SRAM.

[0027] Meanwhile, the pseudo-SRAM in accordance with theabove-conventional technique, it is necessary to pre-charge the bit linefor a subsequent access until a predetermined time (hereinafter referredto as a recovery time TWR) from a time when the write enable signal isinactivated after the write operation to the memory cell has been made.Accordingly, it is difficult for the pseudo-SRAM that the recovery timeTWR becomes zero. The pseudo-SRAM of this conventional techniquemaintains the write operation to the memory cell in a time period thatthe write enable signal is in the active state, for which reason in thistime period, the refresh can be executed.

[0028] For the pseudo-SRAM, a write cycle time TWP has an upper limit ofa write cycle time TWP for the refresh operation.

[0029] The pseudo-SRAM has strict limitations to the recovery time andthe write cycle time, and is different in the specification from thegeneral-purpose SRAM.

[0030] A data write method so called to as “Late Write” has beenpresented for removing the limitations on the specification.

[0031] This late write will, hereinafter, be described briefly. In thememory cycle with an externally given request for the write access, agiven write address and a given write data are merely taken into thesemiconductor memory device, while those write address and write data astaken will be retained in the inside of the semiconductor memory deviceuntil the next request for write operation is entered. The writeoperation to the memory cell is not executed in this memory cycle, butwill be executed in a future memory cycle of the entry of the nextrequest for the write operation to the memory cell. The late write isthat the write operation to the memory cell is delayed to the memorycycle of the entry of the next request for the write operation.

[0032] In accordance with the late write, it is unnecessary to writedata into the memory cell within the memory cycle when these write datahave been taken, for which reason it is unnecessary to pre-charge thebit line after the write operation, thereby allowing the recovery timeTWR to be zero similarly to the general-purpose SRAM. In the latermemory cycle that the data are written into the memory cell, the writeaddress and the write data have already been taken, for which reason theactivation of the write enable signal causes a prompt start the writeoperation to the memory cell. After the data write operation to thememory cell has been made, then it is unnecessary to maintain the wordline to be selected even in the write cycle. This allows allocating asubsequent time period for the refresh. This further makes itunnecessary to limit the write cycle time for ensuring the refreshoperation.

[0033] The use of the late cycle makes it possible that the pseudo-SRAMis operable similarly to the general-purpose SRAM.

[0034] In accordance with the above-described late write, however, it ispossible, in case, that a series of the refresh operation, the readoperation and the write operation appears in a later memory cycle thanthe cycle of the actual write operation, thereby disturbing subsequentoperation in the next memory cycle.

[0035] This problem will be described concretely with reference to FIG.3. FIG. 3 shows a timing of writing data (not illustrated) to addressesA1˜A3.

[0036] In the initial state, the write enable signal /WE is in the highlevel, and the operation mode is the read mode. At a time t110, anaddress ADD is transitioned to an address A1. At a time t112, the writeenable signal /WE is transitioned to the low level, whereby dataexternally designated in the current or present cycle are taken as wellas previous data having already been taken in the previous cycle arestored in late-write to the memory cell.

[0037] At the time t110, the transition of the address ADD appears,whereby the refresh is executed. At a time t111, the refresh isfinished, whereby the read operation is started, Once the read operationhas been started, it is inhibited to interrupt the read operation inview of protecting the data. The above-described late write operation ofthe data win wait for the read operation to be completed. As a result,the late write, which should be executed in the write cycle to theaddress A1, is interrupted into the other write cycle to the nextaddress A2, thereby disturbing the refresh in this next write cycle.

[0038] In accordance with this example, in the write cycle to theaddress A1, a series of the refresh operation, the read operation andthe write operation is executed, thereby causing an increasedconsumption of current.

[0039] The present invention has been made in view of theabove-circumstances. An object of the present invention is to provide asemiconductor memory device allowing the refresh operation to be freefrom any disturbance by the late write and reducing a currentconsumption in a write cycle having the late write operation.

DISCLOSURE OF THE INVENTION

[0040] In order to solve the above-described issues, the presentinvention provides a semiconductor memory device having a memory cellarray comprising memory cells which need refresh and receivingasynchronously a write request and write data together with an accessaddress, wherein the semiconductor memory device comprises an accessmeans for executing a refresh of said memory cell array subsequently toa write cycle to the access address ; a write control means forrendering said access means perform a late write operation, using saidaccess address and said write data given in said memory cycle, after amemory cycle in which said write request has been given ; and a readinhibit control means for inhibiting a read operation based in an outputenable signal in said write cycle having said execution of said latewrite operation.

[0041] In accordance with the present invention, also the semiconductormemory device is so configured as to output retained data which are tobe written through said late write operation if said output enablesignal is activated without any transition of said access address insaid write cycle having said execution of said late write operation.

[0042] In accordance with the present invention, also the semiconductormemory device is so configured as to read out data from a memory cellsubject to an access in a page mode by triggering an output enablesignal in the write cycle.

[0043] In accordance with the present invention, also the semiconductormemory device is so configured as to read out data from a memory celldesignated by the current cycle prior to a refresh in a cycle free ofany read operation.

BRIEF DESCRIPTIONS OF DRAWINGS

[0044]FIG. 1 is a block diagram illustrative of an example of aconfiguration of a semiconductor memory device (pseudo-SRAM) inaccordance with the prior art.

[0045]FIG. 2 is a timing chart describing a refresh operation of thesemiconductor memory device (pseudo-SRAM) in accordance with the priorart.

[0046]FIG. 3 is another timing chart describing a problem with theoperation of the semiconductor memory device (pseudo-SRAM) in accordancewith the prior art.

[0047]FIG. 4 is a timing chart describing a first feature of asemiconductor memory device in accordance with the present invention.

[0048]FIG. 5 is a timing chart describing operations a semiconductormemory device in accordance with the present invention, assuming that asecond feature of the semiconductor memory device is absent.

[0049] PIG. 6 is a timing chart describing a second feature of asemiconductor memory device in accordance with the present invention.

[0050]FIG. 7 is a timing chart describing operations a semiconductormemory device in accordance with the present invention, assuming that athird feature of the semiconductor memory device is absent.

[0051]FIG. 8 is a timing chart describing a third feature of asemiconductor memory device in accordance with the present invention.

[0052]FIG. 9 is a timing chart describing operations a semiconductormemory device in accordance with the present invention, assuming that afourth feature of the semiconductor memory device is absent.

[0053]FIG. 10 is a timing chart describing a fourth feature of asemiconductor memory device in accordance with the present invention.

[0054]FIG. 11 is a timing chart describing operations a semiconductormemory device in accordance with the present invention, assuming thatthe semiconductor memory device has an extension of the fourth feature.

[0055]FIG. 12 is a block diagram illustrative of a feature part of thesemiconductor memory device in accordance with the embodiment of thepresent invention.

[0056]FIG. 13 is a diagram describing a concept of the basic operations(operation based on clock signal ACLK) of the semiconductor memorydevice in accordance with the embodiment of the present invention.

[0057]FIG. 14 is a timing chart describing a write operation of thesemiconductor memory device in accordance with the embodiment of thepresent invention.

[0058]FIG. 15 is a timing chart illustrative of a write operation of thesemiconductor memory device in accordance with the embodiment of thepresent invention.

BEST MODE FOR CARRYING OUT THE INVENTION

[0059] The embodiments of the present invention will be described withreference to the drawings.

[0060] A semiconductor memory device in accordance with the firstembodiment is a pseudo-SRAM configured to perform a refresh operationand a read or write operation in the same cycle, and to allow alate-write operation.

[0061] As long as this point of view is concerned, the semiconductormemory device has the same configuration as that of the prior art shownin FIG. 1.

[0062] Main feature of the semiconductor memory device in accordancewith the embodiment of the present invention will, hereinafter, bedescribed prior to descriptions of the configuration and operationthereof.

[0063] (A) First Feature

[0064] The first feature is to have a function of inhibiting any readoperation in a late write cycle. This first feature is to solve theissue engaged with the above-described prior art. In accordance withthis first feature, an output enable signal /OE is controlled to be inthe high level in the write cycle for inhibiting a read operationsubsequent to refresh.

[0065] Concrete descriptions will be made with reference to FIG. 4. Inan initial state prior to a time t20, the write enable signal /WE andthe output enable signal /OE are in the high level and the low levelrespectively, wherein the semiconductor memory device is in the readmode. At the time t20, a transition of the address ADD is caused tostart a write cycle. Upon this address transition, the word line WL isselected for refresh subsequent to the write operation.

[0066] At a time when a time t0 has past from the time t20, the outputenable signal /OE is transitioned to the high level, wherein the time t0is set smaller than a time tR which is defined from the time t20 to atime t21 when the refresh is finished, whereby the output enable signal/OE is inactivated in the period of time of the refresh. Namely, thetime t0 defined from the time t20 of starting the write cycle throughthe time t0 of transiting the output enable signal /OE into the highlevel is so set as to satisfy the condition of t0<tR. This condition isdefined as the specification. The definition of the output enable signal/OE causes that even the write enable signal /WE is the high level, thenno read operation is started after the refresh has been made, therebyinhibiting this read operation.

[0067] Subsequently, at a time t22, the write enable signal /WE becomeslow level, whereby the late write is executed to cause that the datahaving been taken in the previous write cycle are written into thememory cell. At a time t23, the write enable signal /WE becomes highlevel, data externally designated in this write cycle are taken for alate cycle to be executed in a later write cycle. In this example, theaddress is also transitioned together with the write enable signal /WE,whereby a recovery tWR is set zero.

[0068] At a time t23, the address ADD is transitioned to start the readcycle. Assuming that the semiconductor memory device is thegeneral-purpose SRAM, then even the output enable signal /OE is the highlevel, then the operation of reading data out of the memory cell isexecuted, and the data are placed in the final-stage output buffer. Incontrast, in accordance with the semiconductor memory device of thisembodiment, the high level of the output enable signal /OE ensures noread operation to be started for the reason on the configuration to bedescribed later.

[0069] At a time t24, the output enable signal /OE is transitioned tothe low level, thereby starting the read operation for activating theword line. At a time t25 when a time tOE has past from the time t24,output data DOUT as data DATA are outputted to the outside. In thisexample, the output of the output data DOUT is caused at a time whichcorresponds to an address access time tAA.

[0070] The above-described first feature ensures inhibiting the readoperation in the write cycle. Accordingly, in this write cycle, twotimes of operation of selecting the word line are necessary forexecuting the refresh and the late-write. This ensures that thelate-write does not disturb the operation in the next cycle.

[0071] (B) the Second Feature

[0072] The second feature is to have a function of reading the correctdata even if no transition of the address is caused after thelate-write.

[0073] Page 15

[0074] Prior to the descriptions of this second feature, the readoperation according to the prior art will be described with reference toFIG. 5, wherein no address transition is caused after the late write.

[0075] In FIG. 5, at a time t30, a transition of the address ADD iscaused to start the write cycle, whereby upon the address transition,the refresh is executed. At a time t32, the refresh is finished, wherebythe inhibition to the read operation is caused by the above-describedfirst feature, and data Q0 taken in the previous write cycle are writteninto the memory cell in the late-write.

[0076] At a time t33, the write enable signal /WE becomes high level,whereby input data Q1 are taken, which have been externally designatedas data DARA, for a late-write to be executed in the next write cycle.If no transition of the address ADD is caused and the output enablesignal /OE becomes low level at a time t34, then data Q0 are simplyoutputted to the outside, which are subject to the late-write in thiswrite cycle.

[0077] In view of the outside, data Q0 are designated in this writecycle, for which reason the data Q0 should be outputted by the readoperation without any transition of the address. In accordance with thelate-write, as described-above, data having been taken in the previouswrite cycle are written into the memory cell, whereby data Q0 differentfrom the last-designated data Q1 are outputted. This means that theincorrect data are read out. Accordingly, the introduction of thelate-write needs a different specification from the general-purposeSRAM.

[0078] Taking into account the above-described read operation accordingto the prior art, the second feature of this embodiment will,hereinafter, be described with reference to FIG. 6.

[0079] This second feature is to solve the problem with theabove-described non-correspondence of data. If a request is made forread out operation based on the output enable signal /OE without anyaddress transition in the write cycle, then data which are intended tobe written in the late-write and are held in a register, will beoutputted to the outside with by-passing a normal system of circuitssuch as the memory cell and the sense amplifier.

[0080] Namely, in FIG. 6, at a time t40, a transition of the address ADDis caused, whereby similarly to the above-described case shown in FIG.5, upon the address transition, the refresh and the late-write areexecuted, resulting in that the data Q0 having been taken in theprevious write cycle will be written into the memory cell. At a timet41, the write enable signal /WE becomes high level, so that data Q1currently designated externally will be taken for preparation to thelate-write in the next write cycle.

[0081] Thereafter, no address transition is caused and the output enablesignal /OE becomes low level, whereby the data Q1 taken at the time t41will be outputted from the register holding these data through an outputbuffer, wherein the normal data path is cut in order to avoid anyinterference between the data Q0 subject to the late-write and the dataQ1.

[0082] In order to realize this function, as described below, there areprovided a judgement circuit for detecting the absence of the addresstransition, a by-pass circuit for allowing data output to by-pass thenormal system of circuits and a data-in register for holding data asdesignated externally.

[0083] The above-described second feature allows reading out the datafinally and externally designated even in the read operation without anyaddress transition after the write operation, thereby allowing the readoperation over the same specification as the general-purpose SRAM.

[0084] (C) the Third Feature

[0085] The third feature is to have a function of reading(page-reading), in page mode, correct data even if no address transitionis caused after the late-write.

[0086] Prior to the descriptions for the third feature, the page readoperation free of this third feature will be described with reference toFIG. 7.

[0087] At a time t50, a transition of the address ADD is caused, wherebysimilarly to the above-described case shown in FIG. 6, upon the addresstransition, the refresh and the late-write are executed, and data Q0taken in the previous write cycle will be written into the memory cell.At a time t51, the write enable signal /WE becomes high level, data Q1currently designated externally will be taken to set the data Q1 in adata-in register Dr for preparation to the late-write in the next cycle.Thereafter, no address transition is caused, and at a time t52, theoutput enable signal /OE becomes low level, whereby the data Q1 taken atthe time t51 will be outputted from the data-in register DR through theoutput buffer to the outside. These operations are based on theabove-described second feature.

[0088] Subsequently, at a time t53, transitions of a column address arecaused so that the address ADD shows sequential address transitionsA2˜A4. Data are read out from columns sequentially designated accordingto the column addresses, wherein the data are not read out from thememory cells but simply data (NG) residual on the data bus are read out.This means that the read data are not true data, but incorrect data areread out. It is possible to make an access to the memory cell upon anaddress transition at start for the page read, but it is necessary todistinguish it from the normal read after the refresh. This means itimpossible to achieve a high speed access which is the feature of thepage read.

[0089] With taking into account the above-described page read operation,the third feature of this embodiment will, hereinafter, be describedwith reference to FIG. 8.

[0090] This third feature is to solve the problem with theabove-described page read. If no address transition is caused in thewrite cycle and a request is made for read operation based on the outputenable signal /OE, then parallel read operations of data subject to thepage read will be made for sequential outputs thereof.

[0091] In FIG. 8, at a time t60, the address ADD is transitioned to anaddress A1, whereby similarly to the above-described case shown in FIG.7, upon this address transition, the refresh and the latc-write areexecuted, so that the data Q0 having been taken in the previous writecycle will be written into the memory cell. At a time t61, the writeenable signal /WE becomes high level, data Q1 being currently designatedexternally will be taken (not illustrated) for preparation of alate-write in the next cycle.

[0092] Thereafter, no address transition is caused and at a time t62,the output enable signal /OE becomes low level, whereby the data Q1taken at the time t61 will be outputted from the data-in registerthrough the output buffer to the outside as data for the address A1.Upon transition of the output enable signal /OE, data are read out inparallel from columns corresponding to addresses A2—A4 subsequent to theaddress A1 and then stored in the data register. At a time t63, theaddress ADD is transitioned to the addresses A2—A4, whereby datacorresponding to those addresses will sequentially be outputted from theabove-described data register to the outside.

[0093] The above-described third feature allows a correct read operationof a series of the data including the externally last-designated dataeven if the page read is executed in the absence of the addresstransition after the write operation.

[0094] (D) the Fourth Feature

[0095] The fourth feature is to have a function of a high speed readoperation based on the output enable signal /OE even during the refresh.

[0096] Prior to the descriptions for the fourth feature, the readoperation free of this fourth feature will be described with referenceto FIG. 9.

[0097] At a time t70, a transition of the address ADD is caused, wherebysimilarly to the above-described first through third features, the readoperation is executed based on the output enable signal /OE. If at thetime t70, the refresh is being on the execution by triggering aninternal timer, then the read operation will wait for the finish of therefresh. At a time t71, data DOUT are outputted as data DATA. In thiscase, a read out time tOE based on the output enable signal /OE isdelayed as closely to the address access time tAA.

[0098] With taking into account the above-described read operation basedon the output enable signal, the fourth feature of this embodiment will,hereinafter, be described with reference to FIG. 10.

[0099] This fourth feature is to solve the problem with theabove-described read operation based on the output enable signal. If therefresh is executed by triggering the internal timer in a cycle free ofany data read operation from the memory cell, then the refresh operationfollows to the data read operation from the memory cell.

[0100] In FIG. 10, at a time t80, the address ADD is transitioned to anaddress A1, whereby the output enable signal /OE becomes low level, sothat a read operation of the data DATA will be executed. At a time t81immediately before the output enable signal /OE becomes low level, therefresh is executed by triggering the internal timer, but after the readoperation has been executed for the address A1. Namely, the readoperation is executed by triggering the internal timer before therefresh is then executed.

[0101] Even if a request for the refresh by triggering the internaltimer is made just before the output enable signal /OE becomes lowlevel, then the data DATA are promptly outputted through this readoperation because the read operation has already been started at thetime of the transition of the output enable signal /OE into the lowlevel. Accordingly, the read operation can be made with keeping thepotential high speed performance.

[0102] Even if at a time t83, the output enable signal /OE istransitioned to the low level during the refresh, then the readoperation has been on the execution and the data to be read out havebeen defined, for which reason the high speed read operation can bemade.

[0103] The following descriptions will be made in case that thetransition of the address ADD is caused just after the read operationhas been executed by triggering the internal timer. In this case, asshown in FIG. 11, immediately after the operation has been started at atime t81, then at a time t84, the address ADD is transitioned from theaddress A1 to the address A2, whereby the read operation will beexecuted for the address A2 with the priority over the refreshoperation. Namely, at the time t81, the read operation for the addressA1 is executed by triggering the internal timer for causing the data Q1to be outputted before the read operation for the address A2 is thenexecuted for causing the data Q2 to be outputted, whereby no delay iscaused on the access time tAA to the address A2.

[0104] The first through fourth features of the semiconductor memorydevice in accordance with this embodiment have been described above.

[0105] (Configuration and Operation)

[0106] The configuration and operation of the semiconductor memorydevice in accordance with this embodiment will schematically beillustrated in FIG. 12. In this drawing, an address ADDH and an addressADDL are a higher significant address and a lower significant address.The higher significant address ADDH is an address to be fixed for readoperation in the page mode, and comprises the row address and a part ofthe column address. The lower significant address ADDL is the remainingpart of the column address to be transitioned for the operation in thepage mode.

[0107] A chip select signal /CS is a most significant control signal forcontrolling the semiconductor memory device and for switching a stand-bymode and an active mode. The output enable signal /OE is a controlsignal for enabling an output of data and for controlling an activestate of a data output buffer on a final stage. The write enable signal/WE is a control signal for switching the write mode and the read mode.The semiconductor memory device in accordance with this embodiment dealswith the output enable signal /OE and the write enable signal /WE asinstructions to provide for the operation mode of the circuits.

[0108] An address transition detector circuit 101 detects a transitionof the higher significant address ADDH and outputs a one-shot pulsesignal. A state control circuit 102 takes, therein from the outside,control signals such as the chip select signal /CS and generates andoutputs a read statement RS, a write statement WS, a refresh statementFS, and a clock enable signal CE. This state control circuit 102 is thefeature of this embodiment, and which provides a read inhibition controlmeans for inhibiting a read operation based on the output enable signalin the write cycle with execution of the late-write.

[0109] A clock generator circuit 103 receives the clock enable signal CEand outputs a clock signal ACLK which provides for timings of refreshand read/write in the memory cycle. Descriptions of the clock signalACLK will be made later. A register 104 is to hold the write statementWS by triggering the clock signal ACLK. A logic-AND gate 105 performs anAND-operation of the clock signal ACLK and a logic value of the writestatement held in the register 104 for outputting a clock signal WCLK.

[0110] A register 106 takes and holds, therein, a row address component(X) of the higher significant address ADDH. A hit judgement circuit(HIT) 108 compares the address held in the register 106 to the rowaddress component (X) of the higher significant address ADDH asexternally entered, and outputs a hit signal HX upon correspondencebetween them.

[0111] An n-type MOS transistor 109 is controlled in conductive state inaccordance with the write statement WS, for transferring the output fromthe register 106. An n-type MOS transistor 110 is controlled inconductive state in accordance with the read statement RS, fortransferring the row address component (X) of the higher significantaddress ADDH. An n-type MOS transistor 111 is controlled in conductivestate in accordance with the refresh statement FS, for transferring arefresh address RADD. A register 112 takes and holds, therein, signalstransferred by the above-described n-type MOS transistors 109˜111 andthen outputs a row address AX.

[0112] A system of circuits, comprising a register 113, a hit judgementcircuit 114, n-type MOS transistors 115, 116 and a register 118, doescorrespond to the above-described system of circuits, comprising theregister 106, the hit judgement circuit 108, the n-type MOS transistors109, 111 and the register 112. This system receives an input of a columnaddress (Y) of the higher significant address ADDH, and then outputs acolumn address AY. The hit judgement circuit 114 compares the addressstored in the register 113 to the column address (Y) included in thehigher significant address, and outputs a hit signal HY uponcorrespondence between them. An n-type MOS transistor 117 corresponds tothe above-described n-type MOS transistor 111, and supplies the lowlevel to the register 118 upon output of the refresh statement FS.

[0113] A refresh address generator unit 119 receives a timer clock TMand outputs the refresh address RADD, and which corresponds to theabove-described refresh address generator circuit 8J shown in FIG. 1. Atimer circuit 120 outputs the timer clock at a predetermined timeinterval, and which corresponds to the above-described refresh timercircuit 8G shown in FIG. 1.

[0114] A logic-OR gate 130 performs an OR-operation of the readstatement RS and the refresh statement FS. A register 130 takes andholds, therein, an output from the logic-OR gate 130 by triggering theclock signal ACLK and then outputs a sense amplifier enable signal SE. Abuffer 132 receives an input of the clock signal ACLK and then outputs apre-charge enable signal PE. A register 133 takes and holds, therein,the read statement RS by triggering the clock signal ACLK.

[0115] A memory cell array 140 corresponds to the above-described memorycell array 7 shown in FIG. 1, and which comprises a matrix array of thesame memory cells as DRAM. A data register 141 is to be used in the pagemode, and which comprises latches, the number of which corresponds to adepth of the page. Even illustration is omitted in FIG. 12, the samenumber of the data register 141 as the number of I/O terminals areprovided. In this example, the single data register 141 comprises fourlatches.

[0116] A multiplexer 142 selects data held in the four latches of thedata register 141. An n-type MOS transistor 143 transfers data DQ asselected by the multiplexer 142. An n-type MOS transistor 144 provides aby-path for data. An inverter 145 inverts a signal applied to a gate ofthe n-type MOS transistor 144 and supplies the inverted signal to a gateof the n-type MOS transistor 143. The n-type MOS transistors 143 and 144are complementary controlled in conductive state.

[0117] A data-out buffer 146 supplies the read out data through the I/Oterminal to the outside. An output state, for example, a high impedancestate or a low impedance state of the data-out buffer 146 is controlledbased on the output enable signal /OE. A data-in buffer 147 receives thewrite data through the I/O terminal from the outside. A register 148holds data taken from the outside in the memory cycle, based on thewrite enable signal /WE. A register 149 takes and holds data to bewritten into the memory cell in the late-write, from the above-describeregister 148, by triggering the clock signal WCLK. A switch 150 suppliesthe data held in the register 149 to the memory cell array 140 incorrespondence with the page.

[0118] A system of circuits, comprising a register 134, a hit judgementcircuit 135, n-type MOS transistors 136˜138 and a register 139, doescorrespond to the above-described system of circuits, comprising theregister 113, the hit judgement circuit 114, the n-type MOS transistors115-117 and the register 118. This system receives the lower significantaddress ADDL, and then outputs a column address AY2. The hit judgementcircuit 135 compares the address stored in the register 134 to the lowersignificant address ADDL and outputs a hit signal HY upon correspondencebetween them. A logic-AND gate 160 performs an AND-operation of the hitsignals HX, HY and HP and supplies an output signal from it to theabove-described inverter 145.

[0119] Other than the above-described configuration elements, there arefurther provided an access means for executing a refresh of the memorycell array 140 accompanying to the write cycle to the access address anda write control means for rendering the access means perform thelate-write.

[0120] With reference to FIG. 13, the clock signal ACLK generated by theabove-described clock generator unit 103 will be subsequently described.This clock signal ACLK is asynchronously started (clock start) bytriggering any of the chip select signal /CS, the output enable signal/OE, the write enable signal /WE and the timer clock TM. The startedclock signal ACLK provides for timings of taking and fixing inputsignals such as the chip select signal /CS, the output enable signal /OEand the write enable signal /WE, and also for times of execution of anyof the read statement, the write statement, and the refresh statement.

[0121] At a timing of finishing the statement, the next statement to beexecuted by the next pulse of the clock signal ACLK is decided by thestate control circuit 102. After no further statement to be executed ispresent, then the clock signal ACLK is stopped (clock stop). The clocksignal ACLK provides for the timing necessary for executing the statestatement decided by the state control circuit 102. The clock signalACLK includes pulses providing for timings of fixing the input signalsand pulses providing for timings of executions of the statements.

[0122] An example of the read operation will be described with referenceto FIG. 14.

[0123] At a time t0, a transition of the address ADD is caused, wherebythis address transition is detected by the address transition detectorcircuit 101. Upon this result of detection, the state control circuit102 outputs the clock enable signal CE. The clock generator unit 103receives the input of the clock enable signal CE and then outputs theclock signal ACLK, whereby the clock signal ACLK is started.

[0124] Subsequently, the state control circuit 102 outputs the refreshstatement FS, while each of the input signals is fixed in the eachregister based on the clock signal ACLK For example, the register 112takes, therein, the refresh address RADD through the n-type MOStransistor 111. The register 118 takes, therein, the low level throughthe n-type MOS transistor 117. The register 131 takes, therein, thesignal level (high level) corresponding to the logic value of therefresh statement FS. The register 139 takes, therein, the lowersignificant address ADDL through the n-type MOS transistor 137. In thiscase, since the refresh statement FS has been outputted, the register133 receiving the read statement RS will take, therein, the low level,whereby each latch in the data register 141 is fixed in the inactivestate.

[0125] The respective registers perform outputs of the row address AX,the pre-charge signal PE, the sense amplifier enable signal SE bytriggering a pulse width of the clock signal ACLK for executing aself-refresh operation. Even illustration of the timer clock TM isomitted in FIG. 4, the request for refresh is made based on this timerclock TM.

[0126] Subsequently, at a time t1 of finishing the refresh, the statecontrol circuit 102 judges the next state from the signal levels of thewrite enable signal /WE and the output enable signal /OE, and thenoutputs the read statement RS. At the next rising edge of the clocksignal ACLK, the row address AX and the column address AY are taken forthe read operation, wherein a system of associated circuits is operatedin response to the row address AX and the column address AY, wherebydata are read out of the memory cell and supplied through a bus and theI/O terminals to the outside. At the time t2 of finishing this readoperation, any trigger (such as address transition) providing the nextoperation state is absent, for which reason the state control circuit102 places the clock enable signal CE into the low level, whereby theclock generator unit 103 stops the clock signal ACLK.

[0127] Subsequently, at a time t3, a request is made for refresh bytriggering the timer clock TM, whereby the state control circuit 102generates the clock enable signal CE and the refresh statement FS, andthe clock generator unit 103 generates the clock signal ACLK which fixesthe row address AX for executing the refresh. At a time t4 of finishingthis refresh, any trigger providing the next operation state is absent,for which reason the clock signal ACLK is stopped and the operations areterminated.

[0128] The descriptions of the read operation have been completed above.

[0129] An example of the write operation will be described withreference to FIG. 15.

[0130] At a time t10, the address ADD is transitioned to an address An.This address transition is detected by the address transition detectorcircuit 101. Similarly to the above, the clock enable signal CE isoutputted, and the clock signal ACLK is started. The state controlcircuit 102 outputs the refresh statement FS for executing the refresh.

[0131] Subsequently, at a time t11 of finishing the refresh, the outputenable signal /OE is in the high level while the write enable signal /WEis in the low level, whereby the state control circuit 102 outputs thewrite statement WS. The late-write is executed at the second pulse ofthe clock signal ACLK started upon the transition of the address ADD. Atthis time, the data are written in the late-write, for which reason thewrite operation is completed by the single pulse of the clock signalACLK without depending upon the pulse width of the write enable signal/WE. Subsequently, at a time t12 of finishing the late-write, the outputenable signal /OE is maintained in the high level, while the writeenable signal /WE is maintained in the low level, but the state controlcircuit 102 does not output any statement, whereby the clock signal ACLKis stopped.

[0132] Subsequently, at a time t13, the write enable signal /WE istransitioned to the high level, whereby addresses ADD (ADDH, ADDL) anddata DATA (DIN) to be used in the next write cycle will be taken intothe registers 112, 118, 139 and 148.

[0133] Subsequently, at a time t14, a request is made for refresh bytriggering the timer clock, whereby the clock signal ACLK is risen. Noread operation from the memory cell has been made in the cycle for thisaddress An, for which reason upon the timer clock TM, the state controlcircuit 102 outputs the read statement, whereby the row address AX istaken for executing the read operation, and then data On as data DATAare outputted. At this time, data DIL held in the register 148 aresupplied through the n-type transistor 144 to the data-out buffer 146,whereby the data are then outputted to the outside with by-passing thenormal path such as the switch 150, the data register 141 and themultiplexer 142 (by-pass read).

[0134] Namely, the address ADD (ADDH, ADDL) taken into the registers106, 113 and 134 at the time t13 is compared to the externally enteredaddress ADD by the hit judgement circuit for judging the correspondencebetween them. In this case, no transition of the address ADD has beencaused, for which reason the hit signals HX, HY, and HP will beoutputted. Upon this output, the logic-AND gate 160 supplies the Page 31high level to the gate of the n-type MOS transistor 144 and the inverter145, whereby the n-type MOS transistor 144 turns ON, while the n-typeMOS transistor 143 turns OFF, so that the normal path is disconnectedand the by-pass path is established. The data DIL held in the register148 are supplied through the n-type MOS transistor 144 providing theby-pass path and the data-out buffer 146 to the outside.

[0135] Subsequently, at a time t15 of finishing the read operation, thestate control circuit 102 judges the next state and outputs the refreshstatement FS. At the rising edge of the second pulse of the clock signalACLK, the refresh address RADD is taken as the row address AX forexecuting the refresh.

[0136] At a time t16 of finishing this refresh, any trigger for the nextoperation is absent, for which reason the state control circuit 102inactivates the clock enable signal CE for stopping the clock signalACLK

[0137] The descriptions of the write operation have been made above.

[0138] In accordance with the above-described embodiment, the statecontrol circuit 102 judges the state for outputting the necessarystatement to inhibit the read operation based on the output enablesignal /OE in the write cycle, thereby allowing the late-write to beexecuted following to the refresh.

[0139] In the absence of any transition of the address after thelate-write, the data held in the register in the previous write cycleare outputted through the by-pass path for preventing any miss-read dueto the late-write.

[0140] Data are, in parallel, read out of the memory cells subject tothe page read, by triggering the output enable signal /OE for preventingany miss-read in the page read after the late-write.

[0141] The read operation is made prior to the refresh operation bytriggering the internal timer, for allowing the high speed data readoperation even if the refresh is on the execution by triggering theinternal timer when the output enable signal /OE is activated.

[0142] The present invention should not be limited to theabove-described embodiment. A variety of modifications to the embodimentis available unless the subject of the present invention is changed.

[0143] In accordance with the above-described embodiment, the refreshoperation is started by triggering the address access. Notwithstanding,the refresh operation may be started by triggering the timer. Namely,the present invention is also applicable to the case shown in FIG. 1that the refresh control circuit 8H generates the refresh control signalREFB, based on which the refresh is started by triggering the internalrefresh timer.

[0144] In accordance with the above-described embodiment, such acritical state that the refresh operation is closest to the read/writeoperation would be that the address transition is caused immediatelyafter the refresh has been started based on the refresh control signalREFB. In this case, the read/write operation is executed following tothe refresh operation.

[0145] Accordingly, the refresh operation based on the refresh controlsignal REFB is substantially identical with the refresh operation bytriggering the address access in accordance with the above-describedembodiment.

[0146] Consequently, the present invention is thus applicable to anyrefresh control methods.

[0147] Industrial Applicability:

[0148] As described above, in accordance with the present invention, inthe write cycle with execution of the late-write, the read operation isinhibited based on the output enable signal for preventing thelate-write from disturbing the refresh operation and also for reducing acurrent consumption in the write cycle with execution of the late-write.

What is claimed is:
 1. A semiconductor memory device having a memorycell array comprising memory cells which need refresh and receivingasynchronously a write request and write data together with an accessaddress, wherein the semiconductor memory device comprises: an accessmeans for executing a refresh of said memory cell array subsequently toa write cycle to the access address; a write control means for renderingsaid access means perform a late write operation, using said accessaddress and said write data given in said memory cycle, after a memorycycle in which said write request has been given; and a read inhibitcontrol means for inhibiting a read operation based in an output enablesignal in said write cycle having said execution of said late writeoperation.
 2. The semiconductor memory device as claimed in claim 1,wherein retained data, which are to be written through said late writeoperation, arc read out if said output enable signal is activatedwithout any transition of said access address in said write cycle havingsaid execution of said late write operation.
 3. The semiconductor memorydevice as claimed in claim 1, wherein data are read out from a memorycell subject to an access in a page mode by triggering an output enablesignal in the write cycle.
 4. The semiconductor memory device as claimedin claim 1, wherein data are read out from a memory cell designated bythe current cycle prior to a refresh in a cycle free of any readoperation.